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參數(shù)資料
| 型號(hào)： | MTC-8308 |
| 廠商： | ALCATEL MICROELECTRONICS N V |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 40 MHz, RISC PROCESSOR |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | MTC-8308 |
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MTC-8308
Top Level Description
The top level MTC-8308 body is
shown in figure 3.
The address bus and data bus are 8
bits wide. These busses are the interfa-
ce to external modules. The data bus
is bi-directional. The address bus is an
output from MTC-8308.
If the currently executed instruction is a
load, the signal RE (Read Enable) is
high. The output WE (Write Enable) is
active while a store instruction exe-
cutes.
The power up reset signal, PURST, is
the MTC-8308 reset signal. PURST
must be at least two clock periods
wide. MTC-8308 has four interrupt
request inputs. These signals also have
to be at least two clock periods wide.
There is no limit on the length of these
signals.
MTC-8308 has 5 input and two output
signals for testing. The input signals
are SCAN, SCI1, SCI2, MEMTEST
and TC, and the output signals are
SCO1 and SCO2.
Program ROM and Program
Counter
The program ROM is up to 4096 x 16
and is latched at the output. This
means that the instruction prefetch
register is contained in the program
ROM. The program counter contains a
three level subroutine stack. In addi-
tion to subroutine call, MTC-8308 can
execute both direct and indirect
jumps.
Register File
The register file (REG_FILE) contains
16 general purpose registers. Each
register byte is connected to three
address lines. Two address lines
address the source-bytes and one
addresses the writing location.
Arithmetic, logic and shift operations
read two register bytes and write the
result back into the register file in the
same clock period. The input to
REG_FILE is multiplexed between ALU
output, instruction word and data
input from external modules.
Arithmetic and Logic Unit -
ALU
The ALU performs all arithmetic and
logic byte operations. It is a fully com-
binational block. The ALU reads and
writes to the carryflag in the status
register, STATREG. To make the ALU
as flexible as possible, it is split into 2-
bit-slices. It is therefore easy to recons-
truct the ALU to fit different data-
widths. If the executed instruction is
not an arithmetic or logic one, the A
input to the ALU is zeroed. Input B is
then taken through the ALU without
being affected.
THE BITTEST Module
The BITTEST module executes all bits-
kip and bitcopy instructions. Testing is
done at the ALU output.
Status and Interrupt
Registers -
STATREG and INTREG
MTC-8308 can handle 4 interrupt
signals. The external interrupt request
lines are connected to the data input
of the four least significant bits in
INTREG. In addition to these four bits,
INTREG contains four enable bits. Bit
0 in INTREG (interrupt bit number 0) is
AND-ed with bit 4 (interrupt enable bit
number 0). If the output of this AND
gate is high, the program counter is
forced to address 1. Interrupt 0 is the
interrupt with highest priority. Bits 5, 6
and 7 are enable bits for interrupt 1,
2 and 3 respectively. When one of
these interrupts occurs, the program
counter is forced to address 2.
The STATREG contains status informa-
tion, i.e. the CARRY and ZERO flag.
MTC-8308 Development Kit
Hardware
The MTC-8308 development kit is
designed to be a highly flexible and
powerful tool for specification, design
and prototyping of ASICs built arount
the MTC-8308 core cell. Several func-
tions are implemented to simplify hard-
ware testing and debugging.
By using FPGA (Field Programmable
Gate Array) technology, the MTC-
8308 Development Kit may be indivi-
dually configured to meet the requi-
rements of the actual application to be
designed. Digital I/O modules may
be implemented both within the FPGA
and/or with discrete components on a
separate I/O prototyping board.
The features of the MTC-8308 deve-
lopment kit makes it especially useful
for :
- Software debugging and verifica-
tion;
- Debugging and verification of the
interface between MTC-8308 soft-
ware and application specific I/O
modules;
- Real time emulation of ASIC beha-
vior in system.
A typical ASIC design project would
use the MTC-8308 development kit to
debug and verify the connection bet-
ween MTC-8308 software and I/O
modules. A complete ASIC containing
both analog and digital modules may
thus be emulated in your system in
real time to verify the design before
the actual ASIC processing.
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