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參數(shù)資料
| 型號： | MTC-8308 |
| 廠商： | ALCATEL MICROELECTRONICS N V |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 40 MHz, RISC PROCESSOR |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | MTC-8308 |
3
MTC-8308
ROM
INSTR.REG
DEC
CONTROL
STROBES
RAM
ALU
I/O
DATA BUS
STATREG
INTREG
REG.FILE
IND.ADDR.
DIRECT ADDR.BUS
PC
Fig.1: MTC-8308 Architecture Overview
Fig.2: Memory Map
Architecture
The RISC processor MTC-8308 has an
instruction set of 31 instructions. Most
instructions are handled in one clock
cycle. While an instruction is being
executed, the next instruction is prefet-
ched. Hence the JUMP and SKIP ins-
tructions are executed in two cycles
because of the disposal of the prefet-
ched instruction. LOAD and STORE
with addresses below BF hex (in the
SRAM region) will also be executed in
two cycles because of the SRAM
timing. While writing to or reading
from the I/O-region (addresses above
C0), these instructions will be execu-
ted in only one clock period. The
SRAM can be addressed directly or
indirectly. It is also possible to write
immediate data to one of the 16 gene-
ral purpose registers; it means that
data contained in the instruction word
can be loaded directly into a specified
register.
The MTC-8308 architecture overview
is shown in figure 1. Control strobes
are not drawn to clarify the data and
address paths.
All communication between MTC-
8308 and the I/O modules goes
through the I/O registers. These regis-
ters are addressed in the memory
map. This is a very flexible structure. It
is always possible to add new I/O
modules with new addresses to MTC-
8308. The I/O registers can be read
by LOAD and written to by STORE.
The memory map is shown in figure 2.
Some of the internal connections bet-
ween the main blocks in MTC-8308
are shown in figure 3.
FF
FE
FD
FC
FB
FA
…
EO
DF
…
C0
BF
…
00
JREGH
JREGL
SMAR
INTREG
STATREG
INTERNAL I/O
EXTERNAL I/O
SRAM
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