參數(shù)資料
型號： MT9315
廠商： Zarlink Semiconductor Inc.
英文描述： CMOS Acoustic Echo Canceller
中文描述： 聲學(xué)回聲消除器的CMOS
文件頁數(shù)： 3/30頁
文件大小： 361K
代理商： MT9315
MT9315
Advance Information
2
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
ENA1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input)
. This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins.
Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the MD1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description).
2
MD1
ST-BUS Mode for Rin/Sout (Input)
. When in ST-BUS mode, this pin, in conjunction with the
ENA1 pin, will select the proper ST-BUS mode for Rin/Sout pins (see ST-BUS Operation
description). Connect this pin to Vss in SSI mode.
3
ENA2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input)
.This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the MD2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description).
4
MD2
ST-BUS Mode for Sin/Rout (Input)
.When in ST-BUS mode, this pin in conjunction with the
ENA2 pin, will select the proper ST-BUS mode for Sin/Rout pins (see ST-BUS Operation
description). Connect this pin to Vss in SSI mode.
5
Rin
Receive PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2’s complement linear format. This is the Receive Input
channel from the line (or line) side. Data bits are clocked in following SSI or ST-BUS timing
requirements.
6
Sin
Send PCM Signal Input (Input).
128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2’s complement linear format. This is the Send Input channel (from
the microphone). Data bits are clocked in following SSI or ST-BUS timing requirements.
7
VSS
Digital Ground:
Nominally 0 volt.
8
MCLK
Master Clock (Input):
Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.
9
IC
Internal Connection (Input):
Must be tied to Vss.
10, 11
IC
Internal Connection (Input).
Tie to Vss.
12
LAW
A/
μ
Law Select (Input).
When low, selects
μ
Law companded PCM. When high, selects A-
Law companded PCM. This control is for both serial pcm ports.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
DATA2
CS
VDD
NC
DATA1
IC
IC
IC
NC
NC
SCLK
Sout
Rout
BCLK/C4i
F0i
IC
IC
Sin
VSS
MCLK
Rin
MD2
MD1
ENA2
FORMAT
PWRDN
LAW
ENA1
M
M
E
E
B
I
I
IC
IC
IC
Sin
VSS
Rin
F
L
P
N
N
S
C
DATA2
VDD
NC
DATA1
Sout
Rout
F0i
PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3
2
1
2
2
2
1
1
1
1
1
1
1
PDIP
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