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參數(shù)資料
| 型號： | MT9315 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS Acoustic Echo Canceller |
| 中文描述： | 聲學回聲消除器的CMOS |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MT9315 |
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Advance Information
MT9315
19
Address:
16h Read
Receive (Rin) Peak Detect Register
1 (RIPD1)
Power Up
Reset 00h
RIPD
0
RIPD
1
RIPD
2
RIPD
3
RIPD
4
RIPD
5
RIPD
6
RIPD
7
These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see
Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.
Address:
17h Read
Receive (Rin) Peak Detect Register
2 (RIPD2)
Power Up
Reset 00h
RIPD
8
RIPD
9
RIPD
10
RIPD
11
RIPD
12
RIPD
13
RIPD
14
RIPD
15
See Above Description
Address:
18h Read
Receive (Rin) ERROR Peak Detect Register
1 (REPD1)
Power Up
Reset 00h
REPD
0
REPD
1
REPD
2
REPD
3
REPD
4
REPD
5
REPD
6
REPD
7
These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure #1).
The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register
2 and the low byte is in Register 1.
7
6
5
0
4
3
1
2
RIPD
7
LSB
MSB
RIPD
6
RIPD
5
RIPD
4
RIPD
3
RIPD
2
RIPD
1
RIPD
0
7
6
5
0
4
3
1
2
RIPD
15
LSB
MSB
RIPD
14
RIPD
13
RIPD
12
RIPD
11
RIPD
10
RIPD
9
RIPD
8
7
6
5
0
4
3
1
2
REPD
7
LSB
MSB
REPD
6
REPD
5
REPD
4
REPD
3
REPD
2
REPD
1
REPD
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT933 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933TP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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