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參數(shù)資料
| 型號： | MT9315 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS Acoustic Echo Canceller |
| 中文描述： | 聲學(xué)回聲消除器的CMOS |
| 文件頁數(shù)： | 22/30頁 |
| 文件大小： | 361K |
| 代理商： | MT9315 |
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Advance Information
MT9315
21
Address:
36h Read
Send (Sin) Peak Detect Register
1 (SIPD1)
Power Up
Reset 00h
SIPD
0
SIPD
1
SIPD
2
SIPD
3
SIPD
4
SIPD
5
SIPD
6
SIPD
7
These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see
Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.
Address:
37h Read
Send (Sin) Peak Detect Register
2 (SIPD2)
Power Up
Reset 00h
SIPD
8
SIPD
9
SIPD
10
SIPD
11
SIPD
12
SIPD
13
SIPD
14
SIPD
15
See above description
Address:
38h Read
Send ERROR Peak Detect Register
1 (SEPD1)
Power Up
Reset 00h
SEPD
0
SEPD
1
SEPD
2
SEPD
3
SEPD
4
SEPD
5
SEPD
6
SEPD
7
These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2
(see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high
byte is in Register 2 and the low byte is in Register 1.
7
6
5
0
4
3
1
2
SIPD
7
LSB
MSB
SIPD
6
SIPD
5
SIPD
4
SIPD
3
SIPD
2
SIPD
1
SIPD
0
7
6
5
0
4
3
1
2
SIPD
15
LSB
MSB
SIPD
14
SIPD
13
SIPD
12
SIPD
11
SIPD
10
SIPD
9
SIPD
8
7
6
5
0
4
3
1
2
SEPD
7
LSB
MSB
SEPD
6
SEPD
5
SEPD
4
SEPD
3
SEPD
2
SEPD
1
SEPD
0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT9315AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933TP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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