參數(shù)資料
型號: MT90826AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Quad Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.65 MM PITCH, MS-022DD-1, MQFP-160
文件頁數(shù): 41/46頁
文件大小: 571K
代理商: MT90826AL
MT90826
Data Sheet
41
Zarlink Semiconductor Inc.
Note:
1. High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
2. Register write timing refers to the rising edge of DS at the end of the write cycle.
3. Memory write timing refers to the falling edge of DS at the beginning of the write cycle.
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min. Typ. Max.
Units
Test Conditions
1
CS setup from DS falling
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
DDR
t
DHR
0
ns
2
R/W setup from DS falling
10
ns
3
Address setup from DS falling
2
ns
4
CS hold after DS rising
0
ns
5
R/W hold after DS rising
2
ns
6
Address hold after DS rising
10
ns
7
Data setup from DTA Low on Read
27
ns
C
L
=150pF
C
L
=150pF, R
L
=1K
Note 1
8
Data hold on read
12
20
ns
9
Data setup on write (register write
2
)
Valid Data Delay on write (memory write
3
)
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
t
DSW
0
ns
10
t
SWD
50
85
185
ns
ns
ns
11
Data hold on write
t
DHW
t
AKD
13
ns
12a Acknowledgment Delay: Register RD or WR
55
ns
C
L
=150pF
12b Acknowledgment Delay: Memory RD or WR
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
t
AKD
100
140
240
ns
ns
ns
C
L
=150pF
13
Acknowledgment Hold Time
t
AKH
24
ns
C
L
=150pF, R
L
=1K,
Note 1
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