參數(shù)資料
型號: MT90826AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Quad Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.65 MM PITCH, MS-022DD-1, MQFP-160
文件頁數(shù): 22/46頁
文件大?。?/td> 571K
代理商: MT90826AL
MT90826
Data Sheet
22
Zarlink Semiconductor Inc.
Figure 5 - Example for Frame Alignment Measurement
F0i
FEi Input
(FD9 = 0, sample at internal C32i low phase)
Offset Value
(FD[8:0] = 06
H
, frame offset of six C32i clock cycles)
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Internal
CLK
Frame Boundary
at 32 MHz
master clock
For 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes
F0i
FEi Input
(FD9 = 0, sample at internal C16i low phase)
Offset Value
(FD[8:0] = 03
H
, frame offset of three C16i clock cycles)
1
0
2
3
4
5
6
7
Internal
CLK
at 16 MHz
master clock
For 4 Mbps and 2&4 Mbps modes
8
F0i
FEi Input
(FD9 = 1, sample at internal C8i high phase)
Offset Value
(FD[8:0] = 02
H
, frame offset of two C8i clock cycles)
1
0
2
3
4
Internal
CLK
at 8 MHz
master clock
For 2 Mbps mode
(16.384 MHz)
(16.384 MHz)
(16.384 MHz)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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