參數(shù)資料
型號(hào): MT9072
廠商: Mitel Networks Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 135/269頁
文件大?。?/td> 778K
代理商: MT9072
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Advance Information
MT9072
135
Bit
Name
Functional Description
15
D4YALMI
D4 Yellow Interrupt.
When unmasked this interrupt bit goes high whenever the D4 Yellow alarm
code has been received. This bit is reset after a read of Y35 or Y25.
14
D4Y48I
D4 Y48 Interrupt.
When unmasked this interrupt bit goes high whenever the D4 Yellow alarm
code has been received for 48 msec. This bit is reset after a read of Y35 or Y25.
13
SECYELI
Secondary Yellow Interrupt.
When unmasked this interrupt bit goes high whenever a
Secondary Yellow alarm is received. This bit is reset after a read of Y35 or Y25.
12
ESFYELI
ESF Yellow Interrupt.
When unmasked this interrupt bit goes high whenever a ESF Yellow
alarm is received. This bit is reset after a read of Y35 or Y25.
11
T1DMYI
T1DM Yellow Interrupt.
When unmasked this interrupt bit goes high whenever a TIDM Yellow
alarm is received. This bit is reset after a read of Y35 or Y25.
10
#
not used.
9
BPVI
Bipolar Violation Interrupt.
When unmasked this interrupt bit goes high whenever a bipolar
violation (excluding B8ZS encoding) is encountered. This bit is reset after a read of Y35 or Y25.
8
PRBSI
Pseudo Random Bit Sequence Error Interrupt.
When unmasked this interrupt bit goes high
upon detection of an error with a channel selected for PRBS testing. This bit is reset after a
read of Y35 or Y25.
7
PDVI
Pulse Density Violation Interrupt.
When unmasked this interrupt bit goes high whenever a
sequence of 16 consecutive zeros is received on the line, or the incoming pulse density is less
than N ones in a time frame of 8(N+1) where N = 1 to 23. This bit is reset after a read of Y35 or
Y25.
6
LLEDI
Loop Code Enable Detected Interrupt.
When unmasked this interrupt bit goes high whenever
the loop up code has been detected on the line for a period of 48 milliseconds. This bit is reset
after a read of Y35 or Y25.
5
LLDDI
Loop Code Disable Detected Interrupt.
When unmasked this interrupt bit goes high whenever
the loop down code has been detected on the line for a period of 48 milliseconds. This bit is
reset after a read of Y35 or Y25.
4
BOMI
Bit Oriented Message Interrupt.
When unmasked this interrupt bit goes high whenever a
pattern 111111110xxxxxx0 has been received on the FDL that is different from the last
message. The new message must persist for 8 out the last 10 message positions to be
accepted as a valid new message. Reading this register clears this bit.This bit is reset after a
read of Y35 or Y25.
3
BOMMI
Bit Oriented Message Match Interrupt.
When unmasked this interrupt bit goes high
whenever a pattern 111111110xxxxxx0 has been received on the FDL that is different from
the last message and matches the contents of Bit Oriented Message Match Register. The
new message must persist for 8 out the last 10 message positions to be accepted as a valid
new message. This bit is reset after a read of Y35 or Y25.
2
CASRI
Receive Channel Associated signaling(CAS) Change Interrupt.
When unmasked this
interrupt bit goes high whenever a change of state (optionally debounced - see RSDB in
signaling Control Word) is detected in the signaling bits (AB or ABCD) pattern. This bit is
reset after a read of Y35 or Y25.
1
1SECI
One Second Interrupt Status.
When unmasked this interrupt bit goes high whenever the 1SEC
status bit goes from low to high. This bit is reset after a read of Y35 or Y25.
0
2SECI
Two Second Interrupt Status.
When unmasked this interrupt bit goes high whenever the 2SEC
status bit goes from low to high. This bit is reset after a read of Y35 or Y25.
Table 106 - Receive Line and Timer Interrupt Status (Y35) (T1)
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參數(shù)描述
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