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參數資料
| 型號： | MT8941BP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, MS-018AB, LCC-28 |
| 文件頁數： | 7/27頁 |
| 文件大小： | 491K |
| 代理商： | MT8941BP |
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MT8941B
Data Sheet
7
Zarlink Semiconductor Inc.
Table 3 - Minor Modes of DPLL #2
In FREE-RUN mode, DPLL #2 generates the stand-alone CEPT and ST-BUS timing and framing signals with no
external inputs except the master clock set at 16.384 MHz. The DPLL makes no correction in this configuration and
provides the timing signals without any jitter.
The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT
and ST-BUS compatible timing signals synchronized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE
mode. When SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for
DPLL #1, and thus, an external 1.544 MHz clock signal applied at CVb (pin 21) is divided by DPLL #1 to generate
the internal signal at 8 kHz on to which DPLL #2 locks. Similarly when SINGLE CLOCK-2 mode is selected, DPLL
#1 is in DIVIDE-2 mode, with an external signal of 2.048 MHz providing the internal 8 kHz signal to DPLL #2. In
both these modes, this internal signal is available on C8Kb (pin 10) and DPLL #2 locks to the falling edge to provide
the CEPT and ST-BUS compatible timing signals. This is in contrast to the Normal mode where these timing signals
are synchronized with the falling edge of the 8 kHz signal on C8Kb.
Minor modes of DPLL #2
The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17).
M
S
2
M
S
3
Functional Description
1
1
Provides CEPT/ST-BUS 4.096 MHz and 2.048 MHz clocks and
8kHz frame pulse depending on the major mode selected.
0
1
Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks
depending on the major mode selected while F0b acts as an input.
However, the input on F0b has no effect on the operation of DPLL
#2 unless it is in FREE-RUN mode.
0
0
Overrides the major mode selected and accepts properly phase
related external 4.096 MHz clock and 8 kHz frame pulse to provide
the ST-BUS compatible clock at 2.048 MHz.
1
0
Overrides the major mode selected and accepts a 4.096 MHz
external clock to provide the ST-BUS clock and frame pulse at
2.048 MHz and 8 kHz, respectively.
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相關代理商/技術參數 |
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|---|---|
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
| MT8941BPR | 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8941BPR1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG.TRUNK PLL EOL160209 |
| MT8950 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| MT8950AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
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