參數(shù)資料
型號: MT8941BP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Advanced T1/CEPT Digital Trunk PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 22/27頁
文件大?。?/td> 491K
代理商: MT8941BP
MT8941B
Data Sheet
22
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Please review the section on "Jitter Performance and Lock-in Range".
Figure 17 - Master Clock Inputs
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 14)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
C
L
O
C
K
S
Master clocks input rise time
t
r
t
f
10
ns
2
Master clocks input fall time
10
ns
3
Master clock period
(12.352 MHz)*
t
P12
80.943
80.958
80.974
ns
For DPLL #1, while
operating to provide the
T1 clock signal.
4
Master clock period
(16.384MHz)*
t
P16
61.023
61.035
61.046
ns
For DPLL #2, while
operating to provide the
CEPT and ST-BUS timing
signals.
5
Duty Cycle of master clocks
45
50
55
%
6
Lock-in Range
DPLL #1
DPLL #2
-2.33
-1.69
+2.33
+1.69
Hz
With the Master frequency
tolerance at
±
32 ppm.
AC Electrical Characteristics
-
Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 18)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
F0b input pulse width (LOW)
t
WFP
t
P4o
t
FS
t
FH
244
ns
2
C4b input clock period
244
ns
3
Frame pulse (F0b) setup time
50
ns
4
Frame pulse (F0b) hold time
25
ns
Master clock
inputs
2.4 V
1.5 V
0.4 V
t
r
t
f
t
P12
or t
P16
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