參數(shù)資料
型號: MT8941BP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡
英文描述: Advanced T1/CEPT Digital Trunk PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 21/27頁
文件大小: 491K
代理商: MT8941BP
MT8941B
Data Sheet
21
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
-Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 16)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
D
P
L
L
#2
C4b output clock period
t
P4o
t
W4oH
t
W4oL
t
rC4
t
fC4
213
244
275
ns
85 pF Load
2
C4b output clock width (HIGH)
85
159
ns
3
C4b output clock width (LOW)
116
122
ns
4
C4b output clock rise time
6
ns
85 pF Load
5
C4b clock output fall time
6
ns
85 pF Load
6
Frame pulse output delay
(HIGH to LOW) from C4b
t
FPL
0
13
ns
85 pF Load
7
Frame pulse output delay
(LOW to HIGH) from C4b
t
FPH
0
8
ns
85 pF Load
8
Frame pulse (F0b) width
t
WFP
t
4oLH
t
4oHL
225
245
ns
9
C4o delay - LOW to HIGH
0
15
ns
10
C4o delay - HIGH to LOW
0
20
ns
11
C4b to C2o delay (LOW to
HIGH)
t
42LH
0
3
ns
12
C4b to C2o delay (HIGH to
LOW)
t
42HL
0
6
ns
13
C2o clock period
t
P2o
t
W2oH
t
W2oL
t
rC2
t
fC2
t
2oLH
t
2oHL
457
488
519
ns
85 pF Load
14
C2o clock width (HIGH)
207
280
ns
15
C2o clock width (LOW)
238
244
ns
16
C2o clock rise time
6
ns
85 pF Load
17
C2o clock fall time
6
ns
85 pF Load
18
C2o delay - LOW to HIGH
-5
2
ns
19
C2o delay - HIGH to LOW
0
5
7
ns
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