參數(shù)資料
型號: MT8941BP
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Advanced T1/CEPT Digital Trunk PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 23/27頁
文件大小: 491K
代理商: MT8941BP
MT8941B
Data Sheet
23
Zarlink Semiconductor Inc.
Figure 18 - External Inputs on C4b and F0b for the DPLL #2
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 19 - Three State Outputs and Enable Timings
AC Electrical Characteristics
-
Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Refer to Figure 19)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
O
U
T
P
U
T
Delay from Enable to Output
(HIGH to THREE STATE)
t
PHZ
16
ns
85 pF Load
2
Delay from Enable to Output
(LOW to THREE STATE)
t
PLZ
12
ns
85 pF Load
3
Delay from Enable to Output
(THREE STATE to HIGH)
t
PZH
11
ns
85 pF Load
4
Delay from Enable to Output
(THREE STATE to LOW)
t
PZL
50
16
ns
85 pF Load
Enable
Input
Output
LOW to
OFF
Output
HIGH
to OFF
10%
90%
1.3 V
1.3 V
Outputs
Enabled
Outputs
Enabled
Outputs
Disabled
t
PLZ
t
PHZ
t
PZL
t
PZH
t
f
6 ns
t
r
6 ns
3.0 V
2.7 V
1.3 V
0.3 V
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