參數(shù)資料
型號： MT8941AP
廠商： Mitel Networks Corporation
英文描述： CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
中文描述： 意法半導(dǎo)體的CMOS總線⑩家庭高級T1/CEPT數(shù)字集群鎖相環(huán)
文件頁數(shù)： 8/27頁
文件大小： 491K
代理商： MT8941AP
MT8941B
Data Sheet
8
Zarlink Semiconductor Inc.
Table 4 - Summary of Modes of Operation - DPLL #1 and #2
When MS3 is HIGH, DPLL #2 operates in any of the major modes selected by MS0 and MS1. When MS3 is LOW,
it overrides the major mode selected and DPLL#2 accepts an external clock of 4.096 MHz on C4b (pin 13) to
provide the 2.048 MHz clocks (C2o and C2o) and the 8 kHz frame pulse (F0b) compatible with the ST-BUS format.
The mode select bit MS2 controls the direction of the signal on F0b (pin 6).
When MS2 is LOW, the F0b pin is an 8 kHz frame pulse input. This input is effective only when MS3 is also LOW
and pin C4b is fed by a 4.096 MHz clock, which has a proper phase relationship with the signal on F0b (refer Figure
18). Otherwise, the input on pin F0b will have no bearing on the operation of DPLL #2, unless it is in FREE-RUN
mode as selected by MS0 and MS1. In FREE-RUN mode, the input on F0b is treated the same way as the C8Kb
input is in NORMAL mode. The frequency of the signal on F0b should be 16 kHz for DPLL #2 to lock and generate
the ST-BUS compatible clocks at 4.096 MHz and 2.048 MHz.
Mode
#
M
S
0
M
S
1
M
S
2
M
S
3
Operating Modes
DPLL #1
DPLL #2
0
0
0
0
0
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the input
frame pulse (F0i).
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.
1
0
0
0
1
NORMAL MODE
NORMAL MODE:
F0b is an input but has no function in this mode.
2
0
0
1
0
NORMAL MODE
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
3
0
0
1
1
NORMAL MODE
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
4
0
1
0
0
DIVIDE-1 MODE
Same as mode ‘0’.
5
0
1
0
1
DIVIDE-1 MODE
SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.
6
0
1
1
0
DIVIDE-1 MODE
Same as mode 2.
7
0
1
1
1
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
8
1
0
0
0
NORMAL MODE
Same as mode ‘0’.
9
1
0
0
1
NORMAL MODE
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
10
1
0
1
0
NORMAL MODE
Same as mode 2.
11
1
0
1
1
NORMAL MODE
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
12
1
1
0
0
DIVIDE-2 MODE
Same as mode ‘0’.
13
1
1
0
1
DIVIDE-2 MODE
SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.
14
1
1
1
0
DIVIDE-2 MODE
Same as mode 2.
15
1
1
1
1
DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8941B 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
MT8941BE 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL
MT8941BP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL
MT8941BP1 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209
MT8941BPR 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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