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參數(shù)資料
| 型號(hào)： | MT8941AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭高級(jí)T1/CEPT數(shù)字集群鎖相環(huán) |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MT8941AP |
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MT8941B
Data Sheet
13
Zarlink Semiconductor Inc.
Besides the improved jitter performance, the MT8941B differs from the MT8940 in five other areas:
1. Input pins on the MT8941B do not incorporate internal pull-up or pull-down resistors. In addition, the output con-
figuration of the bidirectional C8Kb pin has been converted from an open drain output to a Totem-pole output.
2. The MT8941B includes a no-correction window to filter out low frequency jitter and wander as illustrated in Fig-
ure 4. Consequently, there is no constant phase relationship between reference signal F0i of DPLL # 1 or C8Kb
of DPLL #2 and the output clocks of DPLL #1 or DPLL #2. Figure 4 shows the new phase relationship between
C8Kb and the DPLL #2 output clocks. Figure 8 illustrates an application where the MT8941B cannot replace the
MT8940 and suggests an alternative solution.
3. The MT8941B must be reset after power-up in order to guarantee proper operation, which is not the case for the
MT8940.
4. For the MT8941B, DPLL #2 locks to the falling edge of the C8Kb reference signal. DPLL#2 of the MT8940
locks on to the rising edge of C8Kb.
5. While the MT8940 is available only in a 24 pin plastic DIP, the MT8941B has an additional 28 pin PLCC package
option.
Applications
The following figures illustrate how the MT8941B can be used in a minimum component count approach in
providing the timing and synchronization signals for the Zarlink T1 or CEPT interfaces, and the ST-BUS. The
hardware selectable modes and the independent control over each PLL adds flexibility to the interface circuits. It
can be easily reconfigured to provide the timing and control signals for both the master and slave ends of the link.
Synchronization and Timing Signals for the T1 Transmission Link
Figures 9 and 10 show examples of how to generate the timing signals for the master and slave ends of a T1 link.
At the master end of the link (Figure 9), DPLL #2 is the source of the ST-BUS signals derived from the crystal clock.
The frame pulse output is looped back to DPLL #1 (in NORMAL mode), which locks to it to generate the T1 line
clock. The timing relationship between the 1.544 MHz T1 clock and the 2.048 MHz ST-BUS clock meets the
requirements of the MH89760/760B. The crystal clock at 12.352 MHz is used by DPLL #1 to generate the 1.544
MHz clock, while DPLL #2 (in FREE-RUN mode) uses the 16.384 MHz crystal oscillator to generate the ST-BUS
clocks for system timing. The generated ST-BUS signals can be used to synchronize the system and the switching
equipment at the master end.
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| MT8966 | Integrated PCM Filter Codec |
| MT8966 | Integrated PCM Filter Codec |
| MT8966AS | Integrated PCM Filter Codec |
| MT8981DP1 | ISO-CMOS ST-BUS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
| MT8941BPR | 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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