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參數(shù)資料
| 型號： | MT8930CP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Subscriber Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQCC44 |
| 封裝： | PLASTIC, MS-018AC, LCC-44 |
| 文件頁數(shù)： | 25/41頁 |
| 文件大?。?/td> | 2516K |
| 代理商： | MT8930CP |
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Data Sheet
MT8930C
25
Table 18. TE Mode Status Register
(2)
(Read Add. 01001
B
)
Note 1:
Bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250
μ
s. It is reset when 128
consecutive ones are received.
The Status Register is updated internally once every ST-BUS frame. Therefore, more than one read access per frame will
return the same value.
Note 2:
Table 19. Master Status Register (Read Add. 10010
B
)
*
These two bits can be used along with status bits IS0 and IS1 to distinguish between states F6/F8 and F4/F5 of the device’s state machine
in TE mode. Please refer to “State Machine” section of Application Note MSAN-141 for further details.
BIT
NAME
DESCRIPTION
B7
Sync/BA
This bit is set if the device has achieved frame synchronization while the activation request
is asserted (DR = 0 and AR = 1). If there is a deactivation request or that AR is low ( DR =
1 or AR = 0), this pin indicates the presence of bus activity
(1)
.
A bus activity identifies the
reception of INFO frames (INFO2 or INFO4).
B6-B5
IS0-IS1
Binary encoded state sequence.
IS0 - IS1
0 - 0
- deactivated
0 - 1
- synchronized
1 - 0
- activation request
1 - 1
- activated
B4
M/S
This bit respresents the state of the received M/S-bit. M when HALF=0 and S when
HALF=1
B3
HALF
The state of this bit identifies which half of the S-Bus frame is currently being output on the
ST-BUS.
B2
RxMFR
A ’1’ when HALF=0 indicates that the multiframe pattern on Fa and N has been detected.
B1
Priority
The status of this bit indicates the internal priority of the device within the designated
priority class. If 1, then it has high priority within the priority class designated in B4 of
control register. If 0, then it has low priority within the priority class designated in B4 of
control register.
B0
DCack
A ’1’ indicates that the device has gained access to the D-channel and has transmitted an
opening flag. This bit is reset to ‘0’ when the closing flag of the last packet in the TxFIFO is
transmitted and the internal priority is reduced from high to low. A collision during
transmission will also reset this bit back to ‘0’.
BIT
NAME
DESCRIPTION
B7-B2
NA
Not available.
B1*
INFO1
In TE mode, this bit is set to ‘1’ only when the device is transmitting INFO1.
Not available in NT mode.
B0*
INFO0
In NT or TE mode, this bit is set to ‘1’ only when the device is transmitting INFO0.
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| MT8931C | Subscriber Network Interface Circuit |
| MT8931CE | Subscriber Network Interface Circuit |
| MT8931CP | Subscriber Network Interface Circuit |
| MT8931C-1 | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit |
| MT8931CE | CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8930CPR | 制造商:Microsemi Corporation 功能描述: |
| MT8931B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931BE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931BP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
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