參數(shù)資料
型號: MT8930CE
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Subscriber Network Interface Circuit
中文描述: DATACOM, DIGITAL SLIC, PDIP28
封裝: PLASTIC, MS-011AB, DIP-28
文件頁數(shù): 35/41頁
文件大?。?/td> 2516K
代理商: MT8930CE
Data Sheet
MT8930C
35
Timing is over recommended temperature & power supply voltages
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 24 - Intel Bus Interface Timing (Write Cycle)
Figure 25 - Intel Bus Interface Timing (Read Cycle)
AC Electrical Characteristics
- Intel Bus Interface Timing (Ref. Figure 24 & 25)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Chip select setup time
t
CSS
10
ns
2
Chip select hold time
t
CSH
25
ns
3
Address Latch pulse width
t
ALW
50
ns
4
Address setup time
t
ADS
20
ns
5
Address hold time
t
ADH
20
ns
6
Data setup time - Write
t
DWS
35
ns
7
Data hold time - Write
t
DHW
20
ns
8
Data output delay - Read
t
DOD
240
ns
50 pF load
9
Data hold time - Read
t
DHR
25
90
ns
50 pF load
10
Write pulse width
t
WPW
60
ns
11
RD, WR delay
t
RWD
60
ns
12
Read pulse width
t
RPW
240
ns
13
Read setup time
t
RDS
20
ns
CS
ALE
AD0-7
WR
RD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Address
Data in
t
CSS
t
CSH
t
ALW
t
ADS
t
ADH
t
RWD
t
DHW
t
WPW
t
RDS
t
DWS
CS
ALE
AD0-7
WR
RD
V
IH
V
IL
V
IH
V
IL
V
I/OH
V
I/OL
V
IH
V
IL
V
IH
V
IL
t
CSH
t
ALW
t
ADS
t
ADH
t
DOD
t
DHR
t
RDS
t
CSS
t
RWD
t
RPW
Address
Data out
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