參數(shù)資料
型號(hào)： MT8930CE
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： Subscriber Network Interface Circuit
中文描述： DATACOM, DIGITAL SLIC, PDIP28
封裝： PLASTIC, MS-011AB, DIP-28
文件頁數(shù)： 19/41頁
文件大小： 2516K
代理商： MT8930CE
Data Sheet
MT8930C
19
Table 5. ST-BUS Control Register (Read/Write Add. 00001
B
)
Note 3: All ST-BUS channels are enabled in controllerless mode.
Table 6. HDLC Control Register 1 (Read/Write Add. 00010
B
)
Note 1: The HDLC receiver must be enabled as well as the designated channel.
BIT
NAME
DESCRIPTION
B7
CH3i
(3)
If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel).
If ’0’, then the channel is disabled, and will read FF
H
.
B6
CH2i
(3)
If ’1’, then the ST-BUS channel 2 input port is enabled (B1-channel).
If ’0’, then the channel is disabled, and will read FF
H
.
B5
CH1i
(3)
If ’1’, then the ST-BUS channel 1 input port is enabled (C-channel).
If ’0’, then the channel is disabled, and will read 00
H
.
B4
CH0i
(3)
If ’1’, then the ST-BUS channel 0 input port is enabled (D-channel).
If ’0’, then the channel is disabled, and will read FF
H
.
B3
CH3o
(3)
If ’1’, then the ST-BUS channel 3 output port is enabled (B2-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
B2
CH2o
(3)
If ’1’, then the ST-BUS channel 2 output port is enabled (B1-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
B1
CH1o
(3)
If ’1’, then the ST-BUS channel 1 output port is enabled (C-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance
B0
CH0o
(3)
If ’1’, then the ST-BUS channel 0 output port is enabled (D-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
BIT
NAME
DESCRIPTION
B7
TxEn
A ’1’ enables the HDLC transmitter for the selected D-channel (i.e., ST-BUS or S-Bus).
A ’0’ disables the HDLC transmitter (i.e., an all 1s signal will be sent).
B6
RxEn
A ’1’ enables the HDLC receiver for the selected D-channel (i.e., ST-BUS or S-Bus).
A ’0’ disables the HDLC receiver (i.e., an all 1s signal will be received).
B5
ADRec
If ’1’, then the address recognition is enabled. This forces the receiver to recognize only
those packets having the unique address as programmed in the Receive Address
Registers or if the address byte is the All-Call address (all 1s).
If ’0’, then the address recognition is disabled and every valid packet is stored in the
received FIFO.
B4
TxPrtSel
This bit selects the port of the HDLC transmitted D-channel.
A’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.
B3
RxPrtSel
This bit selects the port of the HDLC received D-channel.
A ’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.
B2
IFTF
This bit selects the Inter Frame Time Fill.
A ’1’ selects continuous flags. A ’0’ selects an all 1’s idle state.
B1
NA
Keep at ’0’ for normal operation.
B0
HLoop
A ’1’ will activate the HDLC loopback where the transmitted D-channel is looped back to
the received D-channel
(1)
. In NT mode, the transmission of the packet is not affected. In
TE Mode, however, the DReq bit of C-channel Control Register must be set to ‘1’ for the
packet to be transmitted to the S-Bus.
A ’0’ disables the loopback.
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