參數(shù)資料
型號: MT88L85
廠商: Mitel Networks Corporation
英文描述: 3V Integrated DTMF Transceiver with Power-Down and Adaptive Micro Interface(3V 集成雙音多頻信號(DTMF)接收器(帶電源關(guān)閉和自適應(yīng)微接口))
中文描述: 3V的集成雙音多頻收發(fā)器關(guān)閉電源和自適應(yīng)微型接口(3V的集成雙音多頻信號(DTMF)的接收器(帶電源關(guān)閉和自適應(yīng)微接口))
文件頁數(shù): 2/25頁
文件大?。?/td> 197K
代理商: MT88L85
MT88L85
4-72
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
24
28
1
2
3
1
2
4
IN+
IN-
GS
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
Oscillator
input. This pin can also be driven directly by an external clock. CMOS
compatible.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register
A (CRA) is set to low. Requires resistive termination to Vss.
13 R/W
(
WR
)
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
14
CS
Chip Select
input must be gated externally by either address strobe (AS), valid memory
address (VMA) or address latch enable (ALE) signal, depending on processor used. See
Figure 12. Must not be tied low. CMOS compatible.
15
RS0
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
17
DS
(
RD) (Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
18
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See
Figure 10.
19
PWDN
Power-down
(input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin has no internal
pulldown resistor. Therefore, must be tied to logic low when not used.
21-
24
(Intel). CMOS compatible.
26
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
4
5
6
6
7
8
V
Ref
V
SS
OSC1
7
9
OSC2
10
12
TONE
11
12
13
14
15
16
18-
21
22
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
24 PIN DIP/SSOP
2
4
3
2
1
2
2
5
6
7
8
9
10
11
25
24
23
22
21
20
19
1
1
1
1
1
1
1
NC
NC
VRef
VSS
OSC1
OSC2
NC
G
N
I
I
V
S
E
D3
D2
D1
D0
NC
PWDN
NC
T
R
28 PIN PLCC
C
R
N
D
I
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參數(shù)描述
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