參數(shù)資料
型號(hào): MT88L85
廠商: Mitel Networks Corporation
英文描述: 3V Integrated DTMF Transceiver with Power-Down and Adaptive Micro Interface(3V 集成雙音多頻信號(hào)(DTMF)接收器(帶電源關(guān)閉和自適應(yīng)微接口))
中文描述: 3V的集成雙音多頻收發(fā)器關(guān)閉電源和自適應(yīng)微型接口(3V的集成雙音多頻信號(hào)(DTMF)的接收器(帶電源關(guān)閉和自適應(yīng)微接口))
文件頁數(shù): 10/25頁
文件大?。?/td> 197K
代理商: MT88L85
MT88L85
4-80
Table 3. Internal Register Functions
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
Motorola
Intel
RS0
R/W
WR
RD
FUNCTION
0
0
0
1
Write to Transmit
Data Register
0
1
1
0
Read from Receive
Data Register
1
0
0
1
Write to Control Register
1
1
1
0
Read from Status Register
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
b3
b2
b1
b0
C/R
S/D
RxEN
BURST
ENABLE
Table 6. Control Register A Description
BIT
NAME
DESCRIPTION
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
b1
CP/DTMF
Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (Control
Register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (Control Register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3
RSEL
Register Select. A logic high selects Control Register B for the next write cycle to the
control register address. After writing to Control Register B, the following control register
write cycle will be directed to Control Register A.
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