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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 160/189頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51T-36D |
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9
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
In different addressing modes these address registers function as automatic increment and automatic decrement
(see document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for details).
4.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the
Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This
Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or inter-
rupts are enabled. The Stack Pointer must be set to point above 0x40. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return
address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the
Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clk
CPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
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