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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 132/189頁 |
| 文件大小： | 4133K |
| 代理商： | MT80C51T-36D |
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64
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 11-9.
Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition the OC0A or ICF0
flag is set at the same timer clock cycle as TOV0 is set when either OCR0A or ICR0 is used for defining the TOP
value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com-
pare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCR0x Registers are written.
The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0
Register is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICR0 value written is lower than the current value of
TCNT0. The result will then be that the counter will miss the compare match at the TOP value. The counter will
then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. The OCR0A Register however, is double buffered. This feature allows the OCR0A I/O location to be written
anytime. When the OCR0A I/O location is written the value written will be put into the OCR0A Buffer Register. The
OCR0A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle
the TCNT0 matches TOP. The update is done at the same timer clock cycle as the TCNT0 is cleared and the
TOV0 flag is set.
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A
Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCR0A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting the
COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x1:0 to three (see Table 11-3 on page 73). The actual OC0x value will only be visible on the port pin if
the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or
clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the
OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
TCNTn
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
7
Period
2
3
4
5
6
8
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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