參數(shù)資料
型號(hào)： MT58L256V18P1
廠商： Micron Technology, Inc.
英文描述： 256K x 18，Pipelined, SCD SyncBurst SRAM(4Mb，流水線(xiàn)式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 256 × 18，流水線(xiàn)，SCD的SyncBurst的SRAM（4MB，在流水線(xiàn)式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 445K
代理商： MT58L256V18P1
9
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
FBGA PIN DESCRIPTIONS
x18
6R
6P
x32/x36
6R
6P
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P,
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P, 9R,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
5B
4A
–
–
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
7A
7A
BWE#
Input
7B
7B
GW#
Input
6B
6B
CLK
Input
3A
3A
CE#
Input
6A
6A
CE2#
Input
11H
11H
ZZ
Input
3B
3B
CE2
Input
8B
8B
OE#(G#)
Input
9A
9A
ADV#
Input
(continued on next page)
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參數(shù)描述
MT58L256V18P1T-5 制造商:Cypress Semiconductor 功能描述:256KX18 SRAM PLASTIC TQFP 3.3V
MT58L256V18P1T-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L256V32F 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L256V32P 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM
MT58L256V32PF-6 制造商:Cypress Semiconductor 功能描述:256KX32 SRAM PLASTIC FBGA 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk
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