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參數(shù)資料
| 型號(hào)： | MT58L128L36P1T-5 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 481K |
| 代理商： | MT58L128L36P1T-5 |
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3
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
(CE#), two additional chip enables for easy depth ex-
pansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V
VDD power supply, and all inputs and outputs are TTL-
compatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L36P1T-5 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC BGA 3.3V |
| MT58L128L36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-6 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-7.5 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:128K X 36 CACHE SRAM, 4 ns, PQFP100 |
| MT58L128L36P1T-7.5 IT | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC IND TEMP |
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