參數(shù)資料
型號(hào)： MT58L128L36P1T-5
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 128K X 36 CACHE SRAM, 2.8 ns, PQFP100
封裝： PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 481K
代理商： MT58L128L36P1T-5
24
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING
(WRITE timing parameters are contained on the following page.)
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output
data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW#
HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
相關(guān)PDF資料
PDF描述
MT58L512Y36FT-8.5 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
MT58V1MV18DT-10 1M X 18 CACHE SRAM, 5 ns, PQFP100
MT5C2565EC-70/IT 64K X 4 STANDARD SRAM, 70 ns, CQCC28
MT5C256K16B2DJ-12PAT 256K X 16 STANDARD SRAM, 12 ns, PDSO54
MT5C256K16B2DJ-35LAT 256K X 16 STANDARD SRAM, 35 ns, PDSO54
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L128L36P1T-5 TR 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC BGA 3.3V
MT58L128L36P1T-6 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V
MT58L128L36P1T-6 TR 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V
MT58L128L36P1T-7.5 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:128K X 36 CACHE SRAM, 4 ns, PQFP100
MT58L128L36P1T-7.5 IT 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC IND TEMP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*