參數(shù)資料
型號(hào)： MT58L128L32D1
廠商： Micron Technology, Inc.
英文描述： 128K x 32，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 128K的x 32,3.3六/輸出流水線，雙氰胺SyncBurst的SRAM（4MB，在3.3V的輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 425K
代理商： MT58L128L32D1
20
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_2.p65 – Rev 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
D(A1)
NOTE:
1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or
GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices.
-6
-7.5
-10
SYMBOL
t
DS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
DH
t
CEH
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
OEHZ
t
AS
t
ADSS
t
AAS
t
WS
MIN
6.0
MAX
MIN
7.5
MAX
MIN
10
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
166
133
100
2.3
2.3
2.5
2.5
3.0
3.0
3.5
4.2
4.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
相關(guān)PDF資料
PDF描述
MT58L128L36D1 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128L32P1 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128L36P1 128K x 36，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128V32P1 128K x 32， Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
MT58L256L18P1 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L128L32D1F-6 制造商:Micron Technology Inc 功能描述:
MT58L128L32D1T-10 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT58L128L32D1T10A 制造商:Micron Technology Inc 功能描述:
MT58L128L32D1T-7.5 制造商:Cypress Semiconductor 功能描述:128KX32 SRAM PLASTIC TQFP 3.3V
MT58L128L32DT-75 制造商:Micron Technology Inc 功能描述:
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