參數(shù)資料
型號(hào): MT58L128L32D1
廠商: Micron Technology, Inc.
英文描述: 128K x 32,3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 128K的x 32,3.3六/輸出流水線,雙氰胺SyncBurst的SRAM(4MB,在3.3V的輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁數(shù): 13/24頁
文件大?。?/td> 425K
代理商: MT58L128L32D1
13
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_2.p65 – Rev 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
TRUTH TABLE
OPERATION
ADDRESS
USED
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE# CE2# CE2
H
X
L
X
L
H
L
X
L
H
X
X
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
X
H
X
X
X
H
X
X
X
X
X
H
X
H
X
X
X
H
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP# ADSC# ADV# WRITE# OE#
X
L
L
X
L
X
H
L
H
L
X
X
L
X
L
X
H
L
H
L
H
L
H
H
H
H
X
H
X
H
H
H
X
H
H
H
H
H
X
H
H
X
H
H
H
H
H
X
H
H
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
DESELECTE Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “ Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQas and DQPa. BWb# enables WRITEs to DQbs and DQPb. BWc# enables WRITEs to DQcs
and DQPc. BWd# enables WRITEs to DQds and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
相關(guān)PDF資料
PDF描述
MT58L128L36D1 128K x 36,3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128L32P1 128K x 32,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128L36P1 128K x 36,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128V32P1 128K x 32, Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L256L18P1 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
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