參數(shù)資料
型號(hào)： MT49H16M18C
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁(yè)數(shù)： 18/44頁(yè)
文件大小： 1117K
代理商： MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
18
Write Basic Information
Write accesses are initiated with a WRITE com-
mand, as shown in Figure 11. Row and bank addresses
are provided together with the WRITE command.
During WRITE commands, data will be registered at
both edges of DK according to the programmed burst
length (BL). A WRITE latency (WL) one cycle longer
than the programmed READ latency (RL + 1) is
present, with the first valid data registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent
READ command. Figures 15 and 16 illustrate the tim-
ing requirements for a WRITE followed by a READ for
bursts of two and four, respectively.
Setup and hold times for incoming D relative to the
DK edges are specified as
t
DS and
t
DH. The input data
is masked if the corresponding DM signal is HIGH. The
setup and hold times for data mask are also
t
DS and
t
DH.
Figure 11: WRITE Command
NOTE:
A: address; BA: bank address.
Figure 12: Basic WRITE Burst/DM Timing
Timing Parameters
CK#
CK
WE#
REF#
CS#
A
BA
A(20:0)
BA(2:0)
D
DM
t
DH
t
DS
D0
D1
D2
D3
DKx#
DKx
t
DH
t
DS
t
DH
t
DS
DON’T CARE
WRITE
Latency
Data
masked
Data
masked
CK#
CK
t
CKDK
SYMBOL
-25
-33
-5
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
t
DS
t
DH
0.25
0.3
0.4
ns
0.25
0.3
0.4
ns
t
CKDK
-0.3
0.5
-0.3
1.0
-0.3
1.5
ns
SYMBOL
-25
-33
-5
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
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