參數(shù)資料
型號： MT49H16M18C
廠商： Micron Technology, Inc.
英文描述： 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述： 288Mb二氧化硅約化延遲（延遲DRAM二）
文件頁數(shù)： 17/44頁
文件大?。?/td> 1117K
代理商： MT49H16M18C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
17
Configuration Table
Table 8 shows, for different operating frequencies,
the different RLDRAM configurations that can be pro-
grammed into the mode register. The READ and
WRITE latency (
t
RL and
t
WL) values along with the row
cycle times (
t
RC) are shown in clock cycles as well as in
nanoseconds.
The shaded areas correspond to configurations that
are not allowed.
NOTE:
1. BL = 8 is not available for configuration 1.
Table 8:
RLDRAM Configuration Table
FREQUENCY
SYMBOL
CONFIGURATION
UNIT
cycles
1
1
4
2
6
3
8
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
4
6
8
cycles
5
7
9
cycles
400 MHz
20.0
ns
20.0
ns
22.5
ns
300 MHz
20.0
26.7
ns
20.0
26.7
ns
23.3
30.0
ns
200 MHz
20.0
30.0
40.0
ns
20.0
30.0
40.0
ns
25.0
35.0
45.0
ns
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