參數(shù)資料
型號(hào)： MT48LC4M16A2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 28/55頁(yè)
文件大?。?/td> 1458K
代理商： MT48LC4M16A2
28
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK
n
, COMMAND TO BANK
n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS#CAS# WE#
Any
H
L
L
Idle
L
L
L
L
Row Active
L
L
Read
L
(Auto
L
Precharge
L
Disabled)
L
Write
L
(Auto
L
Precharge
L
Disabled)
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
NOTES
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
7
7
11
10
10
8
10
10
8
9
10
10
8
9
NOTE:
1. This table applies when CKE
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and
t
RP has been met.
Row Active: A row in the bank has been activated, and
t
RCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet termi-
nated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
t
RP is met. Once
t
RP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when
t
RCD is met. Once
t
RCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
(Continued on next page)
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