
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023A – DECEMBER 1999 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dc electrical characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Positive going threshold
2.4
VDD = 3 V
Negative going threshold
1.8
RESET
Threshold voltages
Hysteresis
0.6
V
RESET
Threshold voltages
Positive going threshold
3.3
V
VDD = 5.2 V
Negative going threshold
2.9
Hysteresis
0.4
ILKG
Input leakage current
Excludes OSCIN
1
A
ISTANDBY
Standby current
RESET is LOW
0.05
10
A
IDD
Operating current
VDD = 4.5 V, FCLOCK = 8 MHz
10
mA
ISLEEP (deep)
Deep sleep mode supply current
VDD = 4.5 V, DAC off, ARM set,OSC disabled
0.05
10
A
ISLEEP mid)
Mid sleep mode supply current
VDD = 4.5 V, DAC off, ARM set,OSC enabled
40
60
A
ISLEEP (light)
Light sleep mode supply current
VDD = 4.5 V, DAC off, ARM clear,OSC enabled
60
100
A
RPULLUP
F port pull-up resistance
VDD = 5 V
70
150
k
fCPU
CPU Clock rate
(as programmed)
64
8192
kHz
fRTO trim
Trim deviation
RRTO = 470K, VDD = 4.5V, TA=25°C,
fRTO = 8.192 MHz (PLL setting = 7Ch)
±2
±3
%
fRTO volt
Voltage deviation
RRTO = 470K, VDD = 3.5 to 5.2 V, TA=25°C,
fRTO = 8.192 MHz (PLL setting = 7Ch)
±1.5
%
fRTO temp
Temperature deviation
RRTO = 470K, VDD = 4.5 V, TA=0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7Ch)
–0.1
0.1
%/
°C
fRTO res
Resistance deviation
VDD = 4.5 V, TA=25°C, ROSC = 470K@±1%
fRTO = 8.192 MHz (PLL setting = 7Ch)
±1
%
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
external component absolute values
RRTO
RTO external resistance
TA = 25°C, 1% tolerance
470
k
CPLL
PLL external capacitance
TA = 25°C, 10% tolerance
3300
pF