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參數(shù)資料
| 型號： | MSP50C614 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 8 MHz, MIXED DSP, UUC85 |
| 封裝： | DIE-85 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 142K |
| 代理商： | MSP50C614 |
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023A – DECEMBER 1999 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
A flexible clock generation system enables the software to control the clock over a wide frequency range. The
implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency
between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced
apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a
crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to
provide different levels of power management
The periphery consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one
16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either
high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The
input-only port has a programmable pullup option (70-k
minimum resistance) and a dedicated service
interrupt. These features make the input port especially useful as a key-scan interface.
A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,
and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the C614
periphery is a built in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive
capability. The block diagram appearing in Figure 1–1 gives an overview of the C614 functionality. IMPORTANT:
one bit comparator is not currently supported.
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