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參數(shù)資料
| 型號： | MSP50C614 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 8 MHz, MIXED DSP, UUC85 |
| 封裝： | DIE-85 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 142K |
| 代理商： | MSP50C614 |
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023A – DECEMBER 1999 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
TEST CONDITIONS
MIN
MAX
UNIT
tRESET
Reset low pulse width, while VDD is within specified limits
100
ns
t1WIDTH
Pulse width required prior to a negative transition at pin...PD3, PD5, or PF0...PF7
2
1/FClock
t2WIDTH
Pulse width required prior to a positive transition at pin...PD2 or PD4
2
1/FClock
While these pins are being used as interrupt inputs.
Figure 1. Initialization Timing Diagram
tRESET
Figure 2. MSP50P614 External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
t1WIDTH (PD3, PD5, or F port)
t1WIDTH
t2WIDTH (PD2, or PD4)
t2WIDTH
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