參數(shù)資料
型號(hào)： MSP430P315S
廠商： Texas Instruments, Inc.
英文描述： MIXED SIGNAL MICROCONTROLLERS
中文描述： 混合信號(hào)微處理器
文件頁(yè)數(shù)： 46/70頁(yè)
文件大?。?/td> 1176K
代理商： MSP430P315S
SLAS368D
OCTOBER 2002
REVISED MARCH 2005
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
V
CC
2.2V/3V
MIN
TYP
MAX
UNIT
Reference input
voltage range
DAC12IR=0, (see Notes 1 and 2)
AV
CC
/3
AVcc
AV
CC
+0.2
AVcc+0.2
Ve
REF+
DAC12IR=1, (see Notes 3 and 4)
2.2V/3V
V
DAC12_0 IR=DAC12_1 IR =0
2.2V/3V
20
M
DAC12_0 IR=1, DAC12_1 IR = 0
2.2V/3V
Ri
,
(VREF+)
Ri
(VeREF+)
Reference input
resistance
DAC12_0 IR=0, DAC12_1 IR = 1
2.2V/3V
40
48
56
k
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2.2V/3V
20
24
28
k
NOTES:
1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV
CC
).
2. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
V
E(O)
] / [3*(1 + E
G
)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV
CC
).
4. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
V
E(O)
] / (1 + E
G
).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; V
ref
= V
CC
, DAC12IR = 1 (see Figure 23 and Figure 24)
PARAMETER
TEST CONDITIONS
DAC12AMPx=0
→
{2, 3, 4}
DAC12 on-
DAC12AMPx=0
→
{5, 6}
time
(see Note 1,Figure 23)
DAC12AMPx=0
→
7
DAC12AMPx=2
Settling
DAC12_xDAT =
time,full-scale
80h
→
F7Fh
→
80h
DAC12AMPx=4,6,7
V
CC
2.2V/3V
MIN
TYP
60
MAX
120
UNIT
DAC12_xDAT = 800h,
Error
V(O)
<
±
0.5 LSB
t
ON
2.2V/3V
15
30
μ
s
2.2V/3V
6
12
2.2V/3V
100
200
t
S(FS)
DAC12AMPx=3,5
2.2V/3V
40
80
μ
s
2.2V/3V
15
30
DAC12_xDAT =
3F8h
→
408h
→
3F8h
BF8h
→
C08h
→
BF8h
DAC12AMPx=2
2.2V/3V
5
t
S(C-C)
Settling time,
code to code
DAC12AMPx=3,5
2.2V/3V
2
μ
s
DAC12AMPx=4,6,7
2.2V/3V
1
DAC12AMPx=2
2.2V/3V
0.05
0.12
SR
Slew Rate
DAC12_xDAT =
80h
→
F7Fh
80h
→
DAC12AMPx=3,5
2.2V/3V
0.35
0.7
V/
μ
s
DAC12AMPx=4,6,7
2.2V/3V
1.5
2.7
DAC12AMPx=2
2.2V/3V
10
Glitch energy: full-scale
DAC12_xDAT =
80h
→
F7Fh
80h
→
DAC12AMPx=3,5
2.2V/3V
10
nV-s
DAC12AMPx=4,6,7
2.2V/3V
10
NOTES:
1. R
Load
and C
Load
connected to AV
SS
(not AV
CC
/2) in Figure 23.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AVCC
2
CLoad = 100pF
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1
Conversion 2
+/
1/2 LSB
VOUT
Conversion 3
Glitch
Energy
+/
1/2 LSB
tsettleLH
tsettleHL
= 3 k
Figure 23. Settling Time and Glitch Energy Testing
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