參數(shù)資料
型號(hào): MSP430P315S
廠商: Texas Instruments, Inc.
英文描述: MIXED SIGNAL MICROCONTROLLERS
中文描述: 混合信號(hào)微處理器
文件頁(yè)數(shù): 17/70頁(yè)
文件大?。?/td> 1176K
代理商: MSP430P315S
SLAS368D
OCTOBER 2002
REVISED MARCH 2005
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
USART0
The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered
transmit and receive channels.
The I
2
C support is compliant with the Philips I
2
C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported,
as well as master and slave modes. The USART0 also supports 16-bit-wide I
2
C data transfers and has two
dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I
2
C
mode.
USART1 (MSP430x16x/161x Only)
The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels. With the exception of I2C support, operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
12 - P1.0
Device Input Signal
TACLK
Module Input Name
TACLK
Module Block
Module Output Signal
Output Pin Number
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
13 - P1.1
22 - P2.2
TA0
CCI0B
17 - P1.5
DV
SS
DV
CC
TA1
GND
CCR0
TA0
27 - P2.7
V
CC
CCI1A
14 - P1.2
14 - P1.2
CAOUT (internal)
CCI1B
18 - P1.6
DV
SS
DV
CC
TA2
GND
CCR1
TA1
23 - P2.3
V
CC
CCI2A
ADC12 (internal)
15 - P1.3
15 - P1.3
ACLK (internal)
CCI2B
19 - P1.7
DV
SS
DV
CC
GND
CCR2
TA2
24 - P2.4
V
CC
timer_B3 (MSP430x15x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
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