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參數(shù)資料
| 型號： | MSM82C37B-5GS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 301K |
| 代理商： | MSM82C37B-5GS |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Slave Mode
Item
Symbol
Min.
Max.
Unit
Time from Address Valid or
CS
Leading Edge to
IOR
Leading Edge
Comments
t
AR
(Ta = –40 to +85°C, V
CC
= 4.5 to 5.5 V)
50
—
—
ns
Address Valid Set-up Time
to
IOW
Trailing Edge
CS
Leading Edge Set-up Time
to
IOW
trailing edge
t
AW
130
—
—
ns
t
CW
130
—
—
ns
Data Valid Set-up Time
to
IOW
Trailing Edge
Address or
CS
Hold Time
to
IOR
Trailing Edge
t
DW
130
—
—
ns
t
RA
0
—
—
ns
Data Access Time
to
IOR
Leading Edge
t
RDE
—
—
140
ns
Delay Time to Data Floating Status
from
IOR
Trailing Edge
t
RDF
0
—
70
ns
Supply Power Leading Edge Set-up
time to RESET Trailing Edge
Time to First Active
IOR
or
IOW
from RESET Trailing Edge
t
RSTD
500
—
—
ns
t
RSTS
2t
CY
—
—
ns
RESET Pulse Width
IOR
Pulse Width
t
RSTW
t
RW
300
—
—
ns
200
—
—
ns
Address Hold Time
to
IOW
Trailing Edge
CS
Trailing Edge Hold Time
to
IOW
Trailing Edge
Data Hold Time to
IOW
Trailing Edge
IOW
Pulse Width
t
WA
20
—
—
ns
t
WC
20
—
—
ns
t
WD
t
WWS
30
—
—
ns
160
—
—
ns
Notes: 1. Output load capacitance of 150 (pF).
2.
IOW
and
MEMW
pulse widths of t
CY
– 100 (ns) for normal writing, and 2t
CY
– 100
(ns) for extended writing.
IOR
and
MEMR
pulse widths of 2t
CY
– 50 (ns) for normal
timing, and t
CY
– 50 (ns) for compressed timing.
3. DREQ and DACK signal active level can be set to either low or high. In the timing
chart, the DREQ signal has been set to active-high, and the DACK signal to active-
low.
4. When the CPU executes continuous read or write in programming mode, the
interval during which the read or write pulse becomes active must be set to at least
400 ns.
5.
EOP
is an open drain output. The value given is obtained when a 2.2 k
W
pull-up
resistance is connected to V
CC
.
6. Rise time and fall time are less than 10 ns.
7. Waveform measurement points for both input and output signals are 2.2 V for HIGH
and 0.8 V for LOW, unless otherwise noted.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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