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參數(shù)資料
| 型號： | MSM82C37B-5GS |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大小： | 301K |
| 代理商： | MSM82C37B-5GS |
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Semiconductor
MSM82C37B-5RS/GS/VJS
PROGRAMMING
The MSM82C37B-5 is switched to programming status when the HLDA input and
CS
are both
at low level. In this state,
IOR
is changed to low level with
IOW
held at high level to enable
reading by the CPU, or else
IOW
is changed to low level while
IOR
is held at high level to enable
writing by the CPU. A list of command codes for reading from the MSM82C37B-5 is given in
Table 2, and a list of command codes for writing in the MSM82C37B-5 is given Table 3.
Note:
5 programming, that DMA transfer may be commenced to prevent proper programming.
To prevent this interference, the DMA channel must be masked, or the controller
disabled by the command register, or the system set to as to prevent DREQ becoming
active during the programming.
If a DMA transfer request is received from an I/O device during MSM82C37B-
CS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
3
Read Out Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Other Combinations
A
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
A
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
Internal
First/Last
Flip/Flop
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
￥
￥
￥
Channel 0
Channel 1
Channel 2
Channel 3
Status Register
Temporary Register
Output Data Invalid
Current Address
Register
Current Word Count
Register
Current Address
Register
Current Word Count
Register
Current Address
Register
Current Word Count
Register
Current Word Count
Register
Current Address
Register
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
Table 2 List of MSM82C37B-5 Read Commands
相關PDF資料 |
PDF描述 |
|---|---|
| MSM82C43 | INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2JS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2RS | UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C59A-2GS | PROGRAMMABLE INTERRUPT CONTROLLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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