參數(shù)資料
型號(hào)： MSM82C37B-5GS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： PROGRAMMABLE DMA CONTROLLER
中文描述： 可編程DMA控制器
文件頁(yè)數(shù)： 20/34頁(yè)
文件大小： 301K
代理商： MSM82C37B-5GS
20/33
Semiconductor
MSM82C37B-5RS/GS/VJS
Fixed Priority Mode
In fixed priority mode, channel 0 has the highest priority, followed by channels 1, 2, and 3 in that
order.
Rotating Priority Mode
In rotating priority mode, the order of priority is changed so that the channel where the current
DMA transfer has been completed is given lowest priority. This is to prevent any one channel
from monopolizing the system.
The fixed priority is regained immediately after resetting.
Service Terminated Channel
—
CH
0
CH
1
CH
2
CH
3
Priority Mode
Fixed
Order of Priority
for Next DMA
Highest
Lowest
CH
1
CH
2
CH
3
CH
0
CH
1
Rotating
CH
3
CH
0
CH
1
CH
2
CH
3
CH
2
CH
3
CH
0
CH
1
CH
2
CH
0
CH
1
CH
2
CH
3
CH
0
Table 1 MSM82C37B-5 Priority Decision Modes
Compressed Timing
Setting the MSM82C37B-5 to compressed timing mode enables the S
3
state used in extension of
the read pulse access time to be omitted (if permitted by system structure) for two or three clock
cycle DMA transfers. If the S
3
state is omitted, the read pulse width becomes the same as the
write pulse width with the address updated in S
2
and the read or write operation executed in
S
4
. This mode is disregarded if the transfer is a memory-memory transfer, transfer.
Extended Writing
When this mode is set, the
IOW
or
MEMW
signal which normally appears during the S
3
state
is obtained during the S
2
state, thereby extending the write pulse width. The purpose of this
extended write pulse is to enable the system to accomodate memories and I/O devices where
the access time is slower. Although the pulse width can also be extended by using READY, that
involves the insertion of a SW state to increase the number of states.
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