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參數(shù)資料
| 型號： | MSM7731-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | Multifunction PCM CODEC (Voice Signal Processor) |
| 中文描述： | 多功能的PCM編解碼器（語音信號處理器） |
| 文件頁數(shù)： | 8/43頁 |
| 文件大?。?/td> | 247K |
| 代理商： | MSM7731-01 |
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Semiconductor
MSM7731-01
PCMEI
This is the message signal input pin. Use this pin when a message is output to the speaker on
the acoustic-side. This input signal is shifted at the rising edge of the BCLK signal and then
input. The beginning of digital data is identified on the rising edge of the SYNC signal. The
coding format can be selected as
m
-law PCM or 16-bit linear (2's complement) by the PCMSEL
pin. If the PCMEI pin is not used, set it to a logic "1" if
m
-law PCM has been selected, or a logic
"0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or
short-frame sync by the SYNCSEL pin. Timing is the same as for the PCMI pin (refer to Figure
3). This digital input signal is added internally to the echo canceler output signal. Be careful
of overflow during telephone conversations.
PCMEO
This output pin is for memo recording. Use it with the memo function. This output signal is
synchronized to the rising edge of the BCLK and SYNC signals and then output. When not used
for output, this pin is in the high impedance state. It is also at high impedance during the power-
down reset and the initial modes. The coding format can be selected as
m
-law PCM or 16-bit
linear (2's complement) by the PCMSEL pin. The sync format can be selected as normal-sync
or short-frame-sync by the SYNCSEL pin. Timing is the same as for the PCMO pin (refer to
Figure 3).
SYNCSEL
This is the sync timing selection pin for digital data communication. A logic "0" selects
normal-sync timing and a logic "1" selects short-frame-sync timing. Refer to Figure 3 for the
timing. If the pin setting is changed, reset must be activated by either the
PDN
/
RST
pin or the
PDN/RST bit (CR0-B7).
PCMSEL
This is the coding format selection pin for digital data communication. A logic "1" selects
m
-law
PCM and a logic "0" selects 16-bit linear (2's complement) coding format. When an internal clock
is selected, the BCLK signal determines the output clock frequency. If the digital interface is not
used, set this pin to logic "0" to select 16-bit linear coding format.
Since this pin is logically ORed with the PCMSEL bit (CR11-B1), set the pin to a logic "0" when
controlling by the control register.
If the pin setting is changed, reset must be performed by either the
PDN
/
RST
pin or the PDN/
RST bit (CR0-B7).
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