參數(shù)資料
型號(hào)： MSM7731-01
廠商： OKI SEMICONDUCTOR CO., LTD.
元件分類： Codec
英文描述： Multifunction PCM CODEC (Voice Signal Processor)
中文描述： 多功能的PCM編解碼器（語(yǔ)音信號(hào)處理器）
文件頁(yè)數(shù)： 28/43頁(yè)
文件大?。?/td> 247K
代理商： MSM7731-01
28/43
Semiconductor
MSM7731-01
(1) CR0 (basic operating mode settings)
Note: *4. Initial values are the values set when reset is activated by the
PDN
/
RST
pin. (Initial values are also set in the same manner, except for
CR0-B7, when reset by the PDN/RST bit of B7).
B7.......... Power-down reset
0: power-on,
1: power-down reset
During power-down reset, this device enters the power-down state. At this
time, all control register bits and internal variables are reset. After power-down
reset is released, this device enters the initial mode. This bit is internally ORed
with the inverted
PDN
/
RST
signal.
B6.......... Reset control
At reset, the coefficients for the echo canceler and noise canceler are reset.
Control register contents are preserved. While reset is being processed, there
is no sound. Use this bit in cases where the echo path changes (due to line
switching during a telephone conversation, etc.), or when resuming telephone
communicaion. This bit is internally ORed with the inverted
RST
signal.
B5.......... Line CODEC I/O control
When OFF, the line CODEC is in the power-down state, the line CODEC output
pin is at high impedance and line CODEC input pin is internally processed as
an idle pattern input. This bit is internally ORed with the
LINEEN
pin. When
the line CODEC is not used, this control results in low consumption of electrical
power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
B4.......... SYNC, BCLK output control
When OFF, the SYNC and BCLK output pins are in the high impedance state.
This control is valid when the CLKSEL pin is at a logic "0" and has selected the
internal clock mode. When the SYNC and BCLK clocks are not used externally,
this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
B3.......... PCM I/O control
When OFF, the PCMO output pin is in the high impedance state and the PCMI
input pin is internally processed as an idle pattern input. When the line digital
interface is not used, this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
B2.......... PCME I/O control
When OFF, the PCMEO output pin is in the high impedance state and the
PCMEI input pin is internally processed as an idle pattern input. When not
used for message output and memo recording, this control results in low
consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.
0: normal operation,
1: reset
0: ON,
1: OFF
0: ON,
1: OFF
0: ON,
1: OFF
0: ON,
1: OFF
B7
PDN/RST
0
B6
RST
0
B5
LINEEN
0
B4
CLKEN
0
B3
PCMEN
0
B2
PCMEEN
0
B1
OPE
MCUSEL
0
B0
OPE
ECSEL
0
CR0
Initial value (*4)
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