參數(shù)資料
型號: MSM7731-01
廠商: OKI SEMICONDUCTOR CO., LTD.
元件分類: Codec
英文描述: Multifunction PCM CODEC (Voice Signal Processor)
中文描述: 多功能的PCM編解碼器(語音信號處理器)
文件頁數(shù): 29/43頁
文件大小: 247K
代理商: MSM7731-01
29/43
Semiconductor
MSM7731-01
B1, B0 ... Operating mode selection
(0, 0):
Initial mode
Approximately 200 ms after power-down reset is released, the initial mode is
entered.
Only in this mode can the contents of the internal default value store memory
be modified and CR0-B5 to CR0-B0, CR1-B7, CR11-B1 and CR11-B0 be set. In
this mode, digital signal output pins are at high impedance, digital communication
input pins are internally processed as idle pattern inputs, and neither the echo
canceler nor the noise canceler operates. This mode is skipped when the
MCUSEL pin is "1". This mode is released by setting the modes shown below.
Refer to the flowchart of Figure 5.
(1, 0):
Dual echo canceler mode
The acoustic echo canceler, line echo canceler and other functions can be operated
by control from the control registers. Refer to Figure 6.
The initial setting for cancelable echo delay time is as follows:
Acoustic delay time (Tacoud) = 44 ms
Line delay time (Tlined) = 15 ms
(1, 1):
Single echo canceler mode
The acoustic echo canceler and other functions can be operated by control from
the control registers. Control of the line echo canceler is unnecessary in this
mode. Refer to Figure 7.
(Other): Reserved bit (cannot be used)
Note: The MCUSEL pin is internally ORed with B1, and the ECSEL pin is
internally ORed with B0. To return to the initial mode after it has been
released, activate power-down reset.
Figure 5 Initial Mode Flowchart
Figure 6 Dual Echo Canceler Mode
Power-down reset
Power-down reset release
Set control register
Modify default store memory
Start normal operation
CR0–B1=1
Initial mode
Power-down state
Wait for 200 ms
Control registers are reset
Internal variables are reset
YES
NO
Acoustic
CODEC
Acoustic
Echo
Canceler
Noise
Canceler
Slope
Filter
Line
Echo
Canceler
Line
CODEC
Acoustic
CODEC
Acoustic
Echo
Canceler
Noise
Canceler
Slope
Filter
Line
CODEC
Note:
During the initial mode, the READY bit
(CR11-B7) is "1", at all other times it is "0".
Figure 7 Single Echo Canceler Mode
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