參數(shù)資料
型號(hào)： MSM7731-01
廠商： OKI SEMICONDUCTOR CO., LTD.
元件分類： Codec
英文描述： Multifunction PCM CODEC (Voice Signal Processor)
中文描述： 多功能的PCM編解碼器（語(yǔ)音信號(hào)處理器）
文件頁(yè)數(shù)： 37/43頁(yè)
文件大小： 247K
代理商： MSM7731-01
37/43
Semiconductor
MSM7731-01
(12) CR11 (SYNC power-down control register)
B7.......... Data write flag
1: write enabled,
0: write disabled
After power-down reset is released, this device enters the initial mode.
This bit becomes "1" only during the initial mode, enabling access to the internal
data memory. Checking this bit will detect whether writing by an external
microcomputer is possible.
B6 to B2.......Reserved bits
B1.......... PCM coding format control
This is the coding format selection bit for digital data communication. A logic
"1" selects
m
-law PCM and a logic "0" selects 16-bit linear (2's complement)
coding format. When an internal clock is selected, the BCLK signal determines
the output clock frequency to be used when internal clock is selected.
If the digital interface is not used, set this bit to logic "0" to select 16-bit linear
coding format. Since this bit is ORed with the PCMSEL pin, set this bit to logic
"0" when controlling by the pin. If this bit setting is changed, reset must be
activated by either the
PDN
/
RST
pin or the PDN/RST bit (CR0-B7).
B0.......... SYNC power-down
1: SYNC power-down ON,
This bit turns ON or OFF the function that automatically enters the power-
down reset state when the SYNC signal is fixed to a logic "1" or "0". This function
is valid when the external clock mode has been selected by the CLKSEL pin. If
the SYNC signal is fixed at 8kHz or longer, this device automatically writes a
logic "1" to the control register PDN/RST bit (CR0-B7) and enters the power-
down reset state. For timing details, refer to the electrical characteristics.
Modification of initial values is inhibited
1:
m
-law PCM,
0: 16-bit linear
0: SYNC power-down OFF
(13) CR12 (Reserved register)
B7
READY
0
B6
—
0
B5
—
0
B4
—
0
B3
—
0
B2
—
0
B1
PCMSEL
0
B0
SYPDN
0
CR11
Initial value
B7 to B0.......Reserved bits
Modification of initial value is inhibited.
B7
—
0
B6
—
0
B5
—
0
B4
—
0
B3
—
0
B2
—
0
B1
—
0
B0
—
0
CR12
Initial value
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