參數(shù)資料
型號: MSM7730
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 PITCH, PLASTIC, LQFP-144
文件頁數(shù): 8/20頁
文件大?。?/td> 179K
代理商: MSM7730
s MSM7730 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
14
Oki Semiconductor
MSM7730 REGISTER MAP
The following table lists the registers in the MSM7730.
MSM7730 Register Map
Byte
Offset
Register
Group
Width
(bits)
Register Name
Description
0x00
Configura-
tion
8
Device Configuration
Stores serial EEPROM size and sets host interface and processor interface
modes.
0x10
PCMCIA
8
Configuration Option
Stores interrupt, reset, and configuration index information.
0x12
8
Configuration and Status
Stores general cycle status information, including interrupts and power-
down.
0x00
ISA Host
16
Host Control (H_CTL)
Contains ISA reset, host interface and processor interface interrupt
information
0x02
16
Host Address (H_ADDR)
Contains the address in shared memory to be accessed by the H_DATA
register.
0x04
16
Host Data (H_DATA)
Stores host data information.
0x00
Global Con-
trol
16
Version Number
Contains the MSM7730 version number (0xC3). This register is read-only.
0x02
16
Global Control
Contains mapping information for baseband control registers and MAC/PHY
enables.
0x08
16
Processor Interrupt Control
Contains host interrupt, processor interrupt, and interrupt enable information.
0x0C
EEPROM
16
EEPROM Data
This register is a buffer that contains data being transferred to and from the
EEPROM.
0x0E
16
EEPROM Address Control
Contains EEPROM enable and cycle type information.
0x10
PHY/Radio
16
PHY Configuration
Contains Modem and PHY revision information as well as transmit and
receive status. The 3-bit MSEL field defines the type of modem operation..
0x12
16
Synthesizer Program
Contains the least-significant 16 bits of the 32 bits used for synthesizer
programming. This register is used in conjunction with the other SYN register
located at 0x14.
0x14
16
Synthesizer Program
Contains the most-significant 16 bits of the 32 bit s used for synthesizer
programming. This register is used in conjunction with the other SYN register
located at 0x12.
0x16
16
Radio Control (RAD_CTL)
Contains radio configuration and transmit and receive status information.
0x18
16
Radio Delay (RAD_DLYS)
Contains programmable delay parameters between the TXC[1:0] and RXC1
signals.
0x1A
16
Radio Power (RAD_PWR)
Determines when the TXC2 signal is asserted if the power control word is
selected. Two control bits in the PHY control word of a transmit packet
determine which one of four 8-bit values is used. This register is used in
conjunction with the other PAD_PWR register located at 0x1C.
0x1C
16
Radio Power (RAD_PWR)
Determines when the TXC2 signal is asserted if the power control word is
selected. Two control bits in the PHY control word of a transmit packet
determine which one of four 8-bit values is used. This register is used in
conjunction with the other PAD_PWR register located at 0x1A.
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