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參數(shù)資料
| 型號(hào)： | MSM6542-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| 中文描述： | 實(shí)時(shí)時(shí)鐘周期和報(bào)警輸出 |
| 文件頁(yè)數(shù)： | 49/54頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | MSM6542-01 |
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Semiconductor
MSM6542-01/02/03
116
[Sensing interrupts]
(a) When the DP bit is 0
Interrupt
Y
N
Another IC is
an interrupt
factor
Read C
E
register
Are both IRQ FLAG
1
and IRQ FLAG
2
bits
0
Take action for
IRQ FLAG
1
and
IRQ FLAG
2
(b) When the DP bit is 1
Read C
E
register
ID on CPU side
Take action for IRQ
FLAG
1
and IRQ FLAG
2
Are both IRQ FLAG
1
and IRQ FLAG
2
bits
0
IRQ FLAG
0
= 0
IE on CPU side
Another IC is
an interrupt
factor
Y
N
* 1
ID: Interrupt Disable
Y
N
* 2
N
Y
* 3
IE: Interrupt
Enable
Interrupt
Read C
E
register
Are both IRQ FLAG
1
and IRQ FLAG
2
bits
0
Read C
E
register
*1
When the IRQ FLAG
and
IRQ FLAG
bits are read, they
are cleared. Restoration of
these pins to the open
output status is delayed up
to 122
μ
s. For this reason,
the CPU is interrupt-
disabled --- the CPU cannot
accept interrupts.
*2
When the maximum delay
of 122
μ
s described in *1
elapses, the IRA FLAG
0
bit
is set at 0.
*3
Since hardware output re-
questing an interrupt is re-
stored to the open status,
let the CPU interrupt enable.
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