參數(shù)資料
型號(hào)： MSM6542-01
廠(chǎng)商： OKI SEMICONDUCTOR CO., LTD.
英文描述： REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT
中文描述： 實(shí)時(shí)時(shí)鐘周期和報(bào)警輸出
文件頁(yè)數(shù)： 20/54頁(yè)
文件大小： 378K
代理商： MSM6542-01
Semiconductor
MSM6542-01/02/03
87
c)
IT/PLS
1
(D
2
) (InTerrupt/PuLSe
1
)
This bit determines a mode for periodic output. When the bit is 1, a low-level interrupt
request is output from the INTERRUPT OUT pin for the MSM6542-01/02 or from the
PERIODIC OUT pin for the MSM6542-3. When the bit is 0, a low-level pulse is output. In
this case, the MASK
bit is 0. The output periods of interrupt output and pulse output are
determined by the setting of the C
D
' register.
d)
IT/PLS
2
(D
3
) (InTerrupt/PuLSe
2
)
This bit determines a mode for alarm output. When the bit is 1, a low-level alarm interrupt
request is output from the INTERRUPT OUT pin for the MSM6542-01/02 or from the
ALARM OUT pin for the MSM6542-03. When the bit is 0, a low-level pulse is output. In
this case, the MASK
bit is 0. When the contents of the alarm register match those of the
realtime counter within the range specified by the A-ENABLE register, an output wave-
form is provided.
In the alarm pulse output mode, the low level of a pulse lasts for about 61
μ
s.
C
E
register (Control E register)
a)
IRQ FLAG
1
(D
0
) (Interrupt ReQuest FLAG
1
)
The status of this bit depends on the hardware output, low or open, from the PERIODIC
OUT pin for the MSM6542-3 or INTERRUPT OUT pin which uses carry as a trigger for the
MSM6542-1/2. When hardware output is low, the bit is set at 1. When it is open, the bit
is set at 0.
The IRQ FLAG
bit is mainly used to indicate that there is an interrupt request for the
microcomputer. When the period set by the D
(CY
), D
(CY
), and D
(CY
) bits of the C
D
'
register expires with the D
(MASK
) bit of the C
register set at 0, output from the IN-
TERRUPT OUT pin changes from open to low. At the same time, the IRQ FLAG
1
bit
changes from 0 to 1.
When the D
(IT/PLS
) bit of the C
register is 1 (interrupt mode), the IRQ FLAG
bit remains
at 1 (hardware output is low) until the bit is read. When the bit is read, it is cleared.
However, when the IRQ FLAG
bit is read whithin about 122
μ
s of occurrence of an
interrupt with the D
(DP) bit of the C
' register set at 1, the IRQ FLAG
bit is not cleared
immediately. It is cleared about 122
μ
s after the interrupt occurs. When the bit is read at
least about 122
μ
s after an interrupt occurs, it is cleared immediately.
In the interrupt mode, writing 0 in the IRQ FLAG
1
bit does not clear the bit. When another
interrupt occurs with the bit set at 1, it is ignored.
When the D
(IT/PLS
) bit of the C
register is 0 (periodic pulse output mode), the IRQ
FLAG
bit remains at 1 (hardware output is low) until 0 is written in the bit or the automatic
restoration time determined by the period set by the D
(CY
), D
(CY
), and D
(CY
) bits
of the C
' register expires. When the IRQ FLAG
1
bit is read in the periodic pulse output
mode, it is not cleared.
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