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參數(shù)資料
| 型號(hào)： | MSM6542-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| 中文描述： | 實(shí)時(shí)時(shí)鐘周期和報(bào)警輸出 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 378K |
| 代理商： | MSM6542-01 |
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Semiconductor
MSM6542-01/02/03
89
b)
IRQ FLAG
2
(D
1
) (Interrupt ReQuest FLAG
2
)
The status of this bit depends on the hardware output, low or open, from the ALARM OUT
pin for the MSM6542-03 or INTERRUPT OUT pin which uses a match with a set alarm time
as a trigger for the MSM6542-01/02. When hardware output is low, the bit is set at 1. When
it is open, the bit is set at 1.
The IRQ FLAG
bit is mainly used to indicate that there is an alarm timer interrupt for the
microcomputer. When the time set by alarm registers, A-S
to A-W, and the A-ENABLE
register expires with the D
(MASK
) bit of the C
register set at 0, hardware output changes
from open to low. At the same time, the IRQ FLAG
2
bit changes from 0 to 1.
When the D
(IT/PLS
) bit of the C
register is 1 (alarm interrupt mode), the IRQ FLAG
bit
remains at 1 (hardware output is low) until the bit is read. When the bit is read, it is cleared.
However, when the IRQ FLAG
bit is read within about 122
μ
s of occurrence of an alarm
interrupt with the D
(DP) bit of the C
' register set at 1, the IRQ FLAG
bit is not cleared
immediately. It is cleared about 122
μ
s after the interrupt occurs. When the bit is read at
least about 122
μ
s after an interrupt occurs, it is cleared immediately.
In the alarm interrupt mode, writing 0 in the IRQ FLAG
bit does not clear the bit. When
another interrupt occurs with the bit set at 1, it is ignored.
When the D
(IT/PLS
) bit of the C
register is 0 (alarm pulse output mode), the IRQ FLAG
2
bit remains at 1 (hardware output is low) until 0 is written in the bit or automatic restoration
is performed about 61
μ
s later. When the IRQ FLAG
2
bit is read in the alarm pulse output
mode, it is not cleared.
i)
In the alarm interrupt mode (when the IT/PLS
2
bit is 1)
(i-1)
When DP is 0:
(i-2)
When DP is 1:
The IRQ FLAG
2
bit is read
Alarm interrupt timing
"0"
"1"
"0"
IRQ FLAG
2
IRQ FLAG
0
The IRQ FLAG
2
bit is read
Alarm interrupt timing
"0"
"1"
"0"
IRQ FLAG
2
IRQ FLAG
0
122μs
122μs
"1"
Note:
When the IRQ FLAG
bit is read within the 122
μ
s interval with the
MASK
1
bit set at 1, it is not cleared. The IRQ FLAG
2
bit is cleared after
the 122
μ
s interval ends.
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|---|---|
| MSM6542-02 | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| MSM6542-03 | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
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| MSM6545L | Operatable at 0.9 V and Built-in Buzzer Circuit 4-Bit Microcontroller |
| MSM6545L-XXGS-2K | Operatable at 0.9 V and Built-in Buzzer Circuit 4-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM6542-02 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| MSM6542-02RS | 制造商:ROHM Semiconductor 功能描述: |
| MSM6542-03 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| MSM6544 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:42-DOT LCD DRIVER |
| MSM6544GS-2KR1 | 制造商:ROHM Semiconductor 功能描述: |
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