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參數(shù)資料
| 型號： | MSM6542-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | REAL TIME CLOCK WITH PERIODIC AND ALARM OUTPUT |
| 中文描述： | 實(shí)時(shí)時(shí)鐘周期和報(bào)警輸出 |
| 文件頁數(shù)： | 27/54頁 |
| 文件大小： | 378K |
| 代理商： | MSM6542-01 |
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Semiconductor
MSM6542-01/02/03
94
CY
0
Duty cycle of the low level
when IT/PLS1 = 0
0
0
0
0
1
1
1
1
CY
2
CY
1
1/2
1/2
1/2
1/2
1/2
1/8192
1/491520
1/4915200
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Period
1/1024 s
1/128 s
1/64 s
1/16 s
1/2 s
1 s
1 min
10 min
C
E
’ Register (Control E' Register)
a)
DP (D
0
) (Data Protect bit)
This bit has the following two functions:
i)
Restricts write operation to the IC.
ii)
Prolongs the resetting of the IRQ FLAG
bit when the bit is read within 122
μ
s
of occurrence of a periodic alarm in the periodic interrupt mode. Also prolongs
the resetting the IRQ FLAG
2
bit in the same way in the alarm interrupt mode.
i)
Restriction of write operation
When the DP bit is 0, normal write operation is enabled. When the bit is 1, however,
the IC is write-protected except the BANK 1/0 (D
3
) bit of the C
F
register for which
write operation is always allowed.
The DP bit is designed to protect the registers from extenal noise, particularly
erroneous write signal noise which is generated when the standby power supply
voltage is switched to the system power supply voltage or vice versa. After the
necessary data is written, it is recommended that the DP bit be set at 1 if only read
operation is performed.
ii)
Prolongation of reset of the IRQ FLAG bits
When the IT/PLS
(D
) bit of the C
register is 1 (periodic interrupt mode) with the DP
bit set at 0, reading the C
register clears the IRQ FLAG
bit. This is also true for the
IT/PLS
(D
3
) bit when it is 1 (alarm interrupt mode): reading C
E
register clears the IRQ
FLAG
2
bit.
When the IRQ FLAG
bit is read within about 122
μ
s of occurrence of an interrupt with
the IT/PLS
(D
) bit of the C
register set at 1 (periodic interrupt mode), the IRQ FLAG
1
bit is not cleared immediately. Similarly, the IRQ FLAG
bit is not cleared immediately
when the IT/PLS
2
(D
) bit is 1 (alarm interrupt mode). These IRQ FLAG bits are
cleared about 122
μ
s after an interrupt occurs. When these bits are read at least about
122
μ
s after an interrupt occurs, they are cleared immediately. For more information,
see the description of "C
E
REGISTER."
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