參數(shù)資料
型號(hào)： MSM6255GS-K
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi)： 顯示控制器
英文描述： 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 474K
代理商： MSM6255GS-K
MSM6255
Semiconductor
16/39
– Built-in Bus Averter
The bus averter which switches the address buses A0 - A15 of the CPU with the memory
address buses of the refresh. The refresh memory addresses are output to MA0 - MA15 when
the DIEN pin is set at high level and A0 - A15 are output to MA0 - MA15 when the DIEN pin
is set at low level.
– External Clock Operation
An external clock enables the MSM6255 to operate when the DIV pin is set at high level. Input
the external clock to XT.(Leave XT open.)
When the DIV pin is set at low level, the IC enters the crystal oscillation mode.
– Address Output Floating
MA0 - MA15 and RA0 - RA3 become high impedance when the ADF pin is set at low level.
MA0 - MA15 and RA0 - RA3 become normal impedance when the ADF pin is set at high level.
– Power Down Function
The chip select function becomes enabled for the segment driver by connecting the CEf pin
to the ECLK input of the MSM5279. The power down function is valid only in 4-bit parallel
output mode.
– Refresh Memory Address (MA0 - MA15) Operation
In the horizontal direction, MAxx is counted up at the falling edge of CHf. Upper side is
addressed while CHf is set at low level and lower side is addressed while CHf is set at high
level.
MAxx is counted up even if it exceeds the number of horizontal display characters, but this
does not affect the display since no data is being transferred at the time.
The period in which the data transfer is suspended corresponds to eight characters. When the
period passes, one horizontal cycle is completed and the next cycle is commenced.
Memory address operation in the graphic mode is shown in Fig. 2 and that in the character
mode is shown in Fig. 3.
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