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參數(shù)資料
| 型號： | MSM6255GS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 36/40頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MSM6255GS-K |
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MSM6255
Semiconductor
4/39
PIN DESCRIPTIONS
Address output for displaying RAM.
MA0 - MA15 are high impedance when ADF = "L".
Pin
Symbol
Type
Description
1 - 6
71 - 80
MA0
MA15
O
7
22
A0
A15
I
23
FRP
O
24
LIP
O
25
CEφ
O
26
CLP
O
27
FRMB
O
28
31
LD0
LD3
O
32
VDD
O
33
36
UD0
UD3
O
37
CHφ
O
38
Busy
O
39
DIEN
I
40
ADF
I
41
CS
I
42
RD
I
43
WR
I
44
RES
I
45
52
DB0
DB7
I/O
53
60
RD0
RD7
I
61
64
RA0
RA3
O
65
66
XT
I
67
VSS
70
DIV
I
O
—
Memory address input pins
Frame signal. Synchronization of display
Display data latch signal
Chip enable clock for LCD segment driver
Display data shift clock
Alternate signal output pin
Display data parallel output for lower side
Supply voltage
Display data parallel output, Upper display 4-bit output
(OD1, ED1, OD2 and ED2 outputs)
Character clock
Ready state signal. This signal is used while serial transmission stops.
Display enable signal. When this signal is "H", display is enabled.
Address floating input. When this signal is "L", MA0 - MA15, RA0 - RA3 are high impedance,
and when it is "H", A0 - A15 or a refresh address is output to MA0 - MA15.
Chip select. CS = "L"
Read. Reading data is valid when RD = "L"
Write. Data is written when WR = "H"
Reset. Resets each counter.
8-bit data bus. Common pins for 3-state I/O.
ROM/RAM data input. Dot pattern data for the character generator
Raster address output.
*This output is not used in the graphic mode.
RA0 - RA3 are high impedance when ADF = "L".
X’tal osc. When an external clock is used by setting DIV to "H", feeds it to XT.
Ground pin.
"H" : EXT clock
"L" : Self oscillation
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