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參數(shù)資料
| 型號： | MSM6255GS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MSM6255GS-K |
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MSM6255
Semiconductor
26/39
Z
^
_
`
a
b
CHφ
DIEN
display
RAM
OUT
TC
TL
CPU
LCDC
CPU
LCDC
CPU
LCDC
CPU
LCDC
fetching the
pattern data
M
N
tRAM
tUDS
tUDH
N + 1
M + 1
Fig. 10 Basic Timing of Synchronized Access to Display RAM
PR
DQ
CL Q
PR
DQ
CL Q
PR
DQ
CL Q
PR
DQ
CL Q
WR
DATA LATCH
M-WR
M-RD
DIEN
READY
V-RAM
SELECT
VDD
Fig. 11 Wait Function Controlling Circuit
Display RAM must meet the following condition:
TL > tRAM + tUDS
In writing data into the display RAM, LCDC should be synchronized so that the write pulse
occurs during the period of TC. In reading the pattern data from the CPU, the data of display RAM
should be latched first.
Figure 11 shows the controlling circuit.
Legend
TC
: Period when the address bus is occupied by CPU
TL
: Period when the LCDC fetches the refreshed data
tRAM
: Refresh address delay time + memory access time
tUDS
: Upper side data set-up time
tUDH
: Upper side data hold time
When DIEN is high, MA0 - MA15 output address to the upper side when CHf is low and to the
lower side when CHf is high.
To perform synchronized access method, the timing between DIEN and CHf should be as
described in Figure 10.
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