參數(shù)資料
型號(hào)： MSM6255GS-K
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 474K
代理商： MSM6255GS-K
MSM6255
Semiconductor
27/39
– DIEN
DIEN has to be generated when the display RAM is accessed by Synchronized access method.
(1) When the LCD screen is not split into upper and lower ones
If, for example, an LCD panel with a total of 64 dots in vertical direction is displayed at
1/64 duty, either the upper side data or the lower side data becomes unnecessary, and
then the CHf signal can be used as a DIEN signal.
(2) When the LCD screen is split into upper and lower ones
If 4-bit parallel output mode is set and HP=8, the timing diagram of the dot clock and the
character clock is as shown below.
DIEN signal is generated by XT and CHφ.
DIEN signal generating circuit is shown below.
XT
(dot clock)
CHφ
tCH
When Hp π 8 in the 1-bit serial, 2-bit parallel and 4-bit parallel mode, the relation between
XT and CHφ should be referred to Figures 7 and 8.
D Q
Q
DIEN
CHφ
XT(dot clock)
– Scroll
Paging
Scroll
paging is enabled by setting the display start address to the scroll address register.
(1) Memory address of vertical scroll
paging
Figure 2 shows the memory address when the start address is 0000. When the start address
is set at 0050, the display will be vertically shifted by +1.
By setting the starting address one by one, the screen will scroll vertically.
paging will be performed by setting the start address as 3E80.
(2) Memory address of horizontal scroll
When the starting address is set at 0001 in Figure 2, the display on the screen will be shifted
by +1 byte horizontally. The data shown as 004F in Figure 2 corresponds to the memory
data in the 2nd line shown as 0050.
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